This invention relates to digital/analog converters. In particular, the present invention relates to the design of a segmented current-mode digital/analog (D/A) converter having high dynamic linearity.
According to one embodiment of the present invention, a method for providing a segmented D/A converter includes equalizing a time constant in the MSB segment of the D/A converter and a time constant in the LSB segment. In one embodiment, the equalizing procedure includes adding additional capacitance at a switching terminal. The present invention is suitable for implementation in MOS, bipolar, and other technologies.
In one embodiment of the present invention implemented in an MOS technology, the additional capacitance is provided as capacitance at a drain terminal of a cascode transistor in the MSB segment of the D/A converter and coupled to a fixed potential line, such as a bias voltage. In another embodiment of the present invention, transconductances of switching devices are equalized.
Alternatively, in another embodiment of the present invention, the segmented D/A converter is implemented in a bipolar technology. In that embodiment, the additional capacitance is provided as capacitance at a collector terminal of a cascode transistor in the MSB segment of the D/A converter and coupled to a fixed potential line, such as a bias voltage. In another embodiment of the present invention, transconductances of switching devices are equalized. The method of the present invention finds the smaller one of the time constant in the MSB segment and the time constant of the LSB segment.
A method of the present invention may also equalize a skew time in the MSB segment and a skew time in the LSB segment, or take into consideration necessary correction to secondary sources of parasitic capacitance.